Unified Flux Control Architecture for Fluxonium Qubits
Fluxonium量子比特的统一磁通控制架构
Xianchuang Pan, Jiahui Wang, Tao Zhou, Yanbo Guo, Fei Wang, Ze Zhan, Liang Xiang, Zishuo Li, Lu Ma, Xizheng Ma, Huijuan Zhan, Tao Zhang, Kannan Lu, Xing Zhu, Guicheng Gong, Chunqing Deng, Tenghui Wang
AI总结 本文提出一种通过单一磁通控制通道实现横向和纵向操作、结合频率选择性低温滤波与补偿波形合成来减少硬件开销并保持高保真度的Fluxonium量子比特统一控制架构。
Comments 13 pages, 7 figures
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减少硬件开销同时保持高保真度操作的控制架构对于超导量子处理器的持续扩展至关重要。本文实验实现了一种用于fluxonium量子比特的统一控制架构,其中横向($XY$)和纵向($Z$)操作均通过单个任意波形发生器通道驱动的单一磁通控制通道实现。该架构对共享控制通道提出了竞争性要求,必须同时支持用于重置操作的低频磁通传输,同时强烈衰减量子比特跃迁频率附近的宽带噪声。我们通过频率选择性低温滤波以及补偿波形合成(校正滤波控制线引入的脉冲失真)来应对这一挑战。实验上,该方法保持了超过100 $μ$s的相干时间,同时实现了约98%保真度的主动重置和保真度超过99.99%的20纳秒单量子比特门。我们还进一步演示了基于可重用脉冲原语的FPGA本地指令级波形合成,用于统一磁通控制。这些结果确立了统一磁通控制作为一种可扩展的fluxonium量子比特架构,在保持高保真度操作的同时减少了控制硬件开销。
Control architectures that reduce hardware overhead while maintaining high-fidelity operations are essential for the continued scaling of superconducting quantum processors. Here we experimentally realize a unified control architecture for fluxonium qubits, in which both transverse ($XY$) and longitudinal ($Z$) operations are implemented through a single flux-control channel driven by a single arbitrary waveform generator channel. This architecture imposes competing requirements on the shared control channel, which must simultaneously support low-frequency flux transmission for reset operations while strongly attenuating broadband noise near the qubit transition frequency. We address this challenge through frequency-selective cryogenic filtering together with compensated waveform synthesis that corrects the pulse distortion introduced by the filtered control line. Experimentally, this approach preserves coherence times above 100 $μ$s while enabling active reset with approximately 98% fidelity and 20-ns single-qubit gates with fidelities exceeding 99.99%. We further demonstrate FPGA-native instruction-level waveform synthesis based on reusable pulse primitives for unified flux control. These results establish unified flux control as a scalable architecture for fluxonium qubits that reduces control hardware overhead while preserving high-fidelity operation.